As a kind of semiconductor device, a NAND-type flash memory device having a three-dimensional structure is known. This device has a multilayer film which is configured by forming two layers having different dielectric constants alternately. In manufacturing the device, a plurality of deep holes is formed in the multilayer film by an etching of the multilayer film. This etching method is disclosed in U.S. Patent Application Publication No. 2013-0059450.
Specifically, in the etching method disclosed in U.S. Patent Application Publication No. 2013-0059450, a processing target object having a mask made of amorphous carbon on the multilayer film is exposed to plasma of a processing gas containing CH2F2 gas, N2 gas, and NF3.
In the method in which a plurality of openings such as deep holes is formed in an etching target layer as disclosed in U.S. Patent Application Publication No. 2013-0059450, in order to enhance verticality of a wall surface defining the opening, the etching of the multilayer film is performed while protecting the wall surface or a surface of the mask by a plasma reaction product.